Reducing power consumption in memory devices is becoming more important, particularly in view of their growing use in mobile applications. Moreover, as semiconductor device geometries shrink, leakage current in these devices increases, thereby exacerbating the problem. For example, in a memory array (e.g., random access memory (RAM)) which includes a plurality of bit lines and word lines for selectively accessing one or more memory cells in the memory array, a word line column is responsible for a large portion of the overall leakage current due, at least in part, to the large number of driver circuits employed therein.
Memory arrays typically include row decode circuitry employing a decoder and a word line driver for driving a given word line to a logic high (e.g., “1”) or a logic low (e.g., “0”) voltage level in order to selectively enable read or write access devices associated with a corresponding row of memory cells connected to the given word line. Each row of memory cells in the memory array requires a word line driver to drive the access devices of all the memory cells in that row. Thus, for even moderate size memory arrays, the word line load can be quite large, thereby requiring large word line drivers in order to achieve reasonable memory access times. Unfortunately, leakage current in the driver generally increases with the size of the driver.
One conventional approach to reducing leakage current in a word line driver is to employ a pair of stacked PMOS devices connected to each word line at an intermediate node between the two devices. Specifically, a source of a first p-channel metal-oxide-semiconductor (PMOS) device is connected to a voltage supply of the word line driver, a drain of the first device is connected to a source of a second PMOS device at the intermediate node, a drain of the second device is connected to a voltage return of the circuit, and gates of the two devices are connected to one or more control signals. The methodology of using stacked PMOS devices, however, relies on sub-threshold leakage current to lower a voltage at the intermediate node of the PMOS stack. As a result, it takes a significant amount of time for the intermediate node to equalize to a low-current state following a word line access.
Accordingly, there exists a need for an improved word line driver capable of driving a large load but which does not suffer from one or more of the above-noted problems exhibited by conventional word line drivers.